AUTOACK=0, TMR3CMP_EN=0, XCVSEQ=0, CCAMSK=0, RXMSK=0, CCABFRTX=0, TRCV_MSK=0, TMRTRIGEN=0, TC3TMOUT=0, CCATYPE=0, RX_WMRK_MSK=0, TC2PRIME_EN=0, SEQMSK=0, PROMISCUOUS=0, TMR2CMP_EN=0, TMR1CMP_EN=0, PB_ERR_MSK=0, PLL_UNLOCK_MSK=0, RXACKRQD=0, FILTERFAIL_MSK=0, CRC_MSK=0, TXMSK=0, TMR4CMP_EN=0
PHY CONTROL
| XCVSEQ | Zigbee Transceiver Sequence Selector 0 (0): I (IDLE) 1 (1): R (RECEIVE) 2 (10): T (TRANSMIT) 3 (11): C (CCA) 4 (100): TR (TRANSMIT/RECEIVE) 5 (101): CCCA (CONTINUOUS CCA) |
| AUTOACK | Auto Acknowledge Enable 0 (0): sequence manager will not follow a receive frame with a Tx Ack frame, under any conditions; the autosequence will terminate after the receive frame. 1 (1): sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack frame, assuming other necessary conditions are met. |
| RXACKRQD | Receive Acknowledge Frame required 0 (0): An ordinary receive frame (any type of frame) follows the transmit frame. 1 (1): A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected). |
| CCABFRTX | CCA Before TX 0 (0): no CCA required, transmit operation begins immediately. 1 (1): at least one CCA measurement is required prior to the transmit operation (see also SLOTTED). |
| SLOTTED | Slotted Mode |
| TMRTRIGEN | Timer2 Trigger Enable 0 (0): programmed sequence initiates immediately upon write to XCVSEQ. 1 (1): allow timer TC2 (or TC2’) to initiate a preprogrammed sequence (see XCVSEQ register). |
| SEQMSK | Sequencer Interrupt Mask 0 (0): allows completion of an autosequence to generate a zigbee interrupt 1 (1): Completion of an autosequence will set the SEQIRQ status bit, but a zigbee interrupt is not generated |
| TXMSK | TX Interrupt Mask 0 (0): allows completion of a TX operation to generate a zigbee interrupt 1 (1): Completion of a TX operation will set the TXIRQ status bit, but a zigbee interrupt is not generated |
| RXMSK | RX Interrupt Mask 0 (0): allows completion of a RX operation to generate a zigbee interrupt 1 (1): Completion of a RX operation will set the RXIRQ status bit, but a zigbee interrupt is not generated |
| CCAMSK | CCA Interrupt Mask 0 (0): allows completion of a CCA operation to generate a zigbee interrupt 1 (1): Completion of a CCA operation will set the CCAIRQ status bit, but an zigbee interrupt |
| RX_WMRK_MSK | RX Watermark Interrupt Mask 0 (0): allows a Received Byte Count match to the RX_WTR_MARK threshold register to generate a zigbee interrupt 1 (1): A Received Byte Count match to the RX_WTR_MARK threshold register will set the RXWTRMRKIRQ status bit, but a zigbee interrupt is not generated |
| FILTERFAIL_MSK | FilterFail Interrupt Mask 0 (0): allows Packet Processor Filtering Failure to generate a zigbee interrupt 1 (1): A Packet Processor Filtering Failure will set the FILTERFAIL_IRQ status bit, but a zigbee interrupt is not generated |
| PLL_UNLOCK_MSK | PLL Unlock Interrupt Mask 0 (0): allows PLL unlock event to generate a zigbee interrupt 1 (1): A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but a zigbee interrupt is not generated |
| CRC_MSK | CRC Mask 0 (0): sequence manager ignores CRCVALID and considers the receive operation complete after the last octet of the frame has been received. 1 (1): sequence manager requires CRCVALID=1 at the end of the received frame in order for the receive operation to complete successfully; if CRCVALID=0, sequence manager will return to preamble-detect mode after the last octet of the frame has been received. |
| PB_ERR_MSK | Packet Buffer Error Interrupt Mask 0 (0): Enable Packet Buffer Error to assert a zigbee interrupt 1 (1): Mask Packet Buffer Error from generating a zigbee interrupt |
| TMR1CMP_EN | Timer 1 Compare Enable 0 (0): Don’t allow an Event Timer Match to T1CMP to set TMR1IRQ 1 (1): Allow an Event Timer Match to T1CMP to set TMR1IRQ |
| TMR2CMP_EN | Timer 2 Compare Enable 0 (0): Don’t allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ 1 (1): Allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ |
| TMR3CMP_EN | Timer 3 Compare Enable 0 (0): Don’t allow an Event Timer Match to T3CMP to set TMR3IRQ 1 (1): Allow an Event Timer Match to T3CMP to set TMR3IRQ |
| TMR4CMP_EN | Timer 4 Compare Enable 0 (0): Don’t allow an Event Timer Match to T4CMP to set TMR4IRQ 1 (1): Allow an Event Timer Match to T4CMP to set TMR4IRQ |
| TC2PRIME_EN | Timer 2 Prime Compare Enable 0 (0): Don’t allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ 1 (1): Allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to set TMR2IRQ |
| PROMISCUOUS | Promiscuous Mode Enable 0 (0): normal mode 1 (1): all packet filtering except frame length checking (FrameLength>=5 and FrameLength<=127) is bypassed. |
| TMRLOAD | Event Timer Load Enable |
| CCATYPE | Clear Channel Assessment Type 0 (0): ENERGY DETECT 1 (1): CCA MODE 1 2 (10): CCA MODE 2 3 (11): CCA MODE 3 |
| PANCORDNTR0 | Device is a PAN Coordinator on PAN0 |
| TC3TMOUT | TMR3 Timeout Enable 0 (0): TMR3 is a software timer only 1 (1): Enable TMR3 to abort Rx or CCCA operations. |
| TRCV_MSK | Transceiver Global Interrupt Mask 0 (0): Enable any unmasked interrupt source to assert zigbee interrupt 1 (1): Mask all interrupt sources from asserting zigbee interrupt |